This paper proposes and analyzes experimentally an SSMA (Spread Spectrum Multiple Access) signal transmission over a high speed QPSK (Quadrature Phase Shift Keying) modulated signal to achieve higher transmission efficiency per transponder and to facilitate a lower power transmitter for SSMA signal transmission. The employment of high-coding-gain forward error correction for SSMA-QPSK signals makes it possible to transmit SSMA-QPSK signals over a non-linearly amplified QPSK signal transmission channel. Experimental results show that under the condition of a 20dB less transmission power assignment to SSMA-QPSK signals than QPSK signals, the QPSK signals achieve only 0.5dB Eb/No degradation (at Pe=110-4) by employing coding-rate seven-eighth FEC, and the SSMA-QPSK signals achieve about 7dB Eb/No degradation (at Pe=110-4) by employing coding-rate one-half FEC. The satellite link budget shows that even if the SSMA-QPSK signal transmission generates about 7dB Eb/No degradation, it requires 20 dB less transmission power and it still has an extra margin of 8.5dB compared with the high speed QPSK signals (total relative gain of 28.5dB). Thus, the proposed system makes it possible to realize one-way digital video signal transmission in QPSK mode and both-way digital voice signal transmission over one transponder for business video communication systems.

An exact expression of error rate is developed for maximal ratio combining (MRC) in an independent but not necessarily identically distributed frequency selective Nakagami fading channel taking into account inter-symbol, co-channel and adjacent channel interferences (ISI, CCI and ACI respectively). The characteristic function (CF) method is adopted. While accurate analysis of MRC performance cannot be seen in frequency selective channel taking ISI (and CCI) into account, such analysis for ACI has not been addressed yet. The general analysis presented in this paper solves a problem of past and present interest, which has so far been studied either approximately or in simulations. The exact method presented also lets us obtain an approximate error rate expression based on Gaussian approximation (GA) of the interferences. It is shown, especially while the channel is lightly faded, has fewer multipath components and a decaying delay profile, the GA may be substantially inaccurate at high signal-to-noise ratio. However, the exact results also reveal an important finding that there is a range of parameters where the simpler GA is reasonably accurate and hence, we don't have to go for more involved exact expression.

A channel equalization technique on a time division duplex CDMA/TDMA system for wireless multimedia networks is investigated, and the bit error rate performance of the system is theoretically analyzed. The assumed network connects mobile terminals to a node of ATM based high speed LAN through a radio central unit. Only human interface facilities are implemented into the terminal so that users access integrated services through the node of the network. The uplink (from a mobile terminal to a radio central unit) employs a CDMA scheme to transmit human interface signals and the downlink employs a TDMA scheme to transmit display interface signals. Both the CDMA and the TDMA signals occupy the same frequency band. To mitigate bit error rate degradation due to fading, the radio central unit estimates the impulse response of the channel from the received CDMA signals and subtracts the replica signal to cancel the major intersymbol interference (ISI) component. Numerical results using the Nakagami-m fading model and recent propagation measurements show that the proposed TPC technique compensates the fading attenuation and the proposed CEQ cancels the major ISI component. The bit error rate performance of the downlink with the proposed CEQ is superior to that with the DFE by 12dB of the symbol SNR at the BER=10-6 over a specular channel, and the system with the proposed CEQ achieves a BER=10-6 at the symbol SNR=12dB. Furthermore, the channel equalizer is implemented without increases in complexity of the terminal because all the processing on the equalization is carried out only in the radio central unit.

This paper proposes a novel phase ambiguity resolver with combining a very low power Viterbi decoder employing a scarce state transition scheme to realize cost effective receivers for the PCM sound broadcasting satellite service. The theoretical analyses on phase decision performance show that the proposed resolver achieves the symbol-by-symbol phase detection and decides correctly phases of the demodulated data even if the bit error probability of 710-2. The resolver also reduces the phase decision time to below 1/1000 of that of the conventional resolver. Furthermore, experimental results of the power consumption estimate that the prototype Viterbi decoder consumes only 60mW at the data rate of 24.576Mbit/s.

The DSD (Double Soft Decision) concatenated forward error correction scheme is proposed to realize a higher-coding-gain forward error correction system with simple hardware. The novel scheme soft decision decodes inner codes as well as outer codes. In this scheme, likelihood information from an inner Viterbi decoder is used for the decoding of outer codes. Path memory circuit status 1,0 ratio is newly proposed as a measure of likelihood information and it is shown that this method is the most reliable even though it has the simplest hardware among the alternative likelihood information extracting methods. Computer simulation clarifies that the proposed DSD scheme improves Pe performance to one-third that of the conventional hard decision outer decoding.

This paper analyzes performances of trellis coded(TC) 8PSK modulation in Rician fading channels to optimize parameters of Viterbi decoders. The computer simulation clarifies that when carrier power to multipath power ratio (C/M) equals 10dB, Pe performance with reasonable length interleaving depends on free Euclidean distance (dfree) but not on effective code length(ECL) in a practical range of bit error probability (Pe= 10-3-10-4). In the case of C/M=5dB, the effect of ECL appears in the range of bit energy to noise power density ratio (Eb/No)C/M (=5dB). Therefore, for domestic mobile satellite communication systems for non-high latitude countries, only dfree must be considered for TC8PSK Viterbi decoder design. Moreover, to improve Pe performance in slow fading environment, pre-Viterbi-decoding maximal ratio combining is proposed. The proposed diversity scheme improves required Eb/No to achieve Pe=10-4 by more than 6dB compared with no interleaving and more than 2.5 dB compared with interleaving.

A simple exact error rate analysis is presented for random binary direct sequence code division multiple access (DS-CDMA) considering a general pulse shape and flat Nakagami fading channel. First of all, a simple model is developed for the multiple access interference (MAI). Based on this, a simple exact expression of the characteristic function (CF) of MAI is developed in a straight forward manner. Finally, an exact expression of error rate is obtained following the CF method of error rate analysis. The exact error rate so obtained can be much easily evaluated as compared to the only reliable approximate error rate expression currently available, which is based on the Improved Gaussian Approximation (IGA).

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

This paper proposes a feedback-loop type transmission power control (TPC) scheme coupled with first and second order prediction methods and analyzes the optimum control period and residual control error. In order to minimize residual control error, the three main factors contributing to residual control error are analyzed. First, to detect accurately up-link rain attenuation, a channel quality detection method is proposed and analyzed experimentally for puseudo-error detection. Second, rain attenuation rates in Ka band are measured and analyzed statistically. Finally, the optimum control period of the proposed TPC scheme is analyzed. The simulation results on the prototype TPC system show a maximum of 4.5 dB residual control error is achievable with an optimum control period of about 1 second to 1.5 seconds.

This paper proposes a semi-autonomous frame synchronization scheme for a TDMA (Time Division Multiple Access)-TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization in a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame timing control, and compensates the propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation and analysis results confirm the accurate and stable TDMA frame synchronization of all base stations even in fading environments.

This paper proposes a group demodulator that employs multi-symbol chirp Fourier transform to demodulate pulse shaped and time asynchronous signals without degradation; this is not possible with conventional group demodulators based on chirp Fourier transform. Computer simulation results show that the bit error rate degradation of the proposed group demodulator at BER=10-3 is less than 0.3dB even when a root Nyquist (α=0.5) filter is used as the transmission pulse shaping filter and the symbol timing offset between the desired channel and the chirp sweep is half the symbol period.

This paper proposes a new fully-digitalized π/4-shift QPSK modulator consisting of a digital pulse shaping filter and a baseband quadrature modulator. By employing a novel digital filter configuration, the required filter memory is reduced to just 6.25% of the conventional one. Moreover, since the proposed baseband modulation scheme does not employ analog mixers or an analog 90 divider, a very accurate, high-stable and compact modulator is realized. It is shown that the proposed scheme achieves excellent low power consumption characteristics and is more suitable for digital LSIC implementation of personal communication terminals than a direct RF modulation scheme and an analog IF modulation scheme.

This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.

This paper describes reverse modulation carrier recovery with a tank-limiter for Offset QPSK (OQPSK) burst signals. Acquisition performance is discussed taking into account hardware implementation errors in the carrier recovery circuit. The results indicate hardware implementation errors cause a significant recovered carrier phase error during BTR (Bit Timing Recovery) of OQPSK burst signals. A phase error reduction technique by modifying the BTR code for OQPSK burst signals is proposed to improve the acquisition performance. Computer simulation and hardware experiments confirmed its improvement. The performance of a prototype OQPSK burst demodulator using the proposed carrier recovery scheme is also presented.

A novel wireless multimedia network employing a time division duplex CDMA/TDMA scheme is proposed. The network connects mobile multimedia terminals to an ATM based LAN through a radio central unit, and provides both uplink and downlink with unbalanced data rates in the same frequency band. The uplink (from a mobile terminal to a radio central unit) employs a CDMA scheme to transmit low speed human interface signals (-2.4kbit/s), and the downlink employs a TDMA scheme to transmit high speed video signals (-24Mbit/s). The data rates of both links are independent from that of the LAN. The uplink also employs a RAKE receiver and a forward error correction (FEC) scheme using a BCH code in order to reduce bit errors caused by multipath fading. To mitigate channel degradation caused by the near-far problem and multipath fading, a transmission power control (TPC) method for both links and a channel equalizer (CEQ) for the downlink are proposed. The control signals for the TPC and the CEQ are estimated from the impulse response of the channel which is extracted as the output of the matched filters in the CDMA receiver. Theoretical analyses are performed to evaluate the bit error rate (BER) characteristics of the proposed network. The BER performance is derived for a general multipath fading condition modeled by the Nakagami-m distribution and a typical delay profile. Numerical calculation using recent propagation measurements shows the bit error rates of both uplink and downlink to be less than 10-6 when both of the TPC and the CEQ are employed if there are some specular components in the received signals. This excellent performance can cut a way to realize a mobile multimedia terminal for customer premises. Furthermore, the configuration of the mobile terminal is quite simple even if the high speed TDMA signals are received over a multipath fading channel.

A transmission power control technique on a TDD-CDMA/TDMA system for wireless multimedia networks is proposed. The assumed network connects mobile terminals to a node of an ATM based high speed LAN through a radio central unit. Only human interface facilities are implemented into the terminal so that users access integrated services through the node of the network. The uplink (from a mobile terminal to a radio central unit) employs a CDMA scheme to transmit human interface signals (2.4kbit/s) and the downlink employs a TDMA scheme to transmit display interface signals (24 Mbit/s). Both the CDMA and the TDMA signals occupy the same frequency band. To mitigate bit error rate degradation due to the fading, the radio central unit estimates the impulse response of the channel from the received CDMA signals and controls the transmission power of the TDMA signals to compensate the fading attenuation. The bit error rate performance of the downlink with the proposed transmission power control is theoretically analyzed under several fading conditions. Numerical results using the Nakagami-m fading model and recent propagation measurements show that the proposed power control technique compensates the fading attenuation and improves the bit error rate performances. The bit error rate of the downlink is reduced from 10-2 to 10-5 at the symbol SNR of 20dB by employing the proposed transmission power control, which is less sensitive to the severity of the fading. Furthermore, the proposed transmission power control is implemented without increasing the terminal complexity because all the processing on the power control of the downlink is carried out only in the radio central unit.

In this study, we construct an analytical model to investigate the system throughput of 802.15.3c WPAN by examining hybrid slotted CSMA/CA-TDMA and slotted CSMA/CA multiple access methods. Our analysis clearly shows the differences between the system throughputs of both multiple access methods. The obtained results show that the hybrid slotted CSMA/CA-TDMA can achieve a considerably higher system throughput compared to the slotted CSMA/CA; the difference between the two access methods is especially pronounced as the increase in the number of devices contending for the network increase. The system throughput comparisons have established why the hybrid slotted CSMA/CA-TDMA is preferred over the slotted CSMA/CA for high-speed wireless communications of the 802.15.3c WPAN.

This paper proposes a self frequency preset (SFP) PLL synthesizer to realize a simple frequency preset PLL synthesizer with temperature-resistant and shorter frequency settling time than the conventional temperature un-compensated phase and frequency preset (PFP) PLL synthesizer. Since the proposed synthesizer employs a simple frequency locked loop (FLL) circuit to preset the output frequency at each frequency hopping period, the synthesizer eliminates the need to store f-V characteristic of the VCO in ROM. The frequency settling time of the proposed synthesizer is theoretically and experimentally analyzed. The theoretical analysis using the realistic f-V characteristic of a IF band VCO show that the frequency settling time of the proposed synthesizer is 130µs shorter than that of the conventional PFP PLL synthesizer at 40MHz hopping in the 200MHz band for all temperatures. Furthermore, the experimental results confirm that the frequency acquisition time of a prototype FLL circuit is accordant with the calculated results. Thus, the proposed SFP PLL synthesizer can achieve faster frequency settling than the conventional PFP PLL synthesizer for all temperatures and its simple configuration allows to be easily implemented with existing CMOS ASIC devices.